According to the device specifications, the RTL9210B supports the standard, offering a maximum theoretical bandwidth of 20 Gbps . On the host side, it utilizes a PCIe Gen 3 x2 interface. While the chip is capable of supporting PCIe Gen 3 x4 speeds, the upstream USB 20 Gbps limit renders a x4 interface redundant for throughput, making the x2 configuration the optimal design choice for manufacturers to reduce PCB trace complexity.